1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating it.
Although applicable, in principle, to any semiconductor memory devices, the present invention and the problems on which it is based will be explained with regard to ROM memories or read-only memories using silicon technology.
Known ROM semiconductor memory devices of this type use horizontal or vertical MOSFETs as semiconductor memory cells. A customary method for programming such ROM memories consists in modifying threshold voltages of the MOSFETs used in a ROM cell array in accordance with the desired ROM contents by suitably masked vertical channel implantations. In other words, at least two types of MOSFETs are produced, a first type having a first threshold voltage (e.g. without channel implantation) and a second type having a second threshold voltage (e.g. with channel implantation). One type is assigned the logic “1” and the other type the logic “0”. Programmed in this way, each transistor can store a single bit.
It is a constant aim in memory development to increase the storage density, that is to say the number of bits that can be stored per unit area or unit volume. One approach in this direction is the continual miniaturization of the structures involved, for example through read only memories (ROM) memories having folded trench structures.
A further approach is in modifying the semiconductor memory elements in such a way that they can each store more than one bit. This can be achieved for example by performing more than one type of channel implantation, with the result that one bit can be stored per memory cell for each channel implantation.
By way of example, four different threshold voltages, that is to say 2 bits per memory cell, can be generated by four different channel implantations. The different threshold voltages can be distinguished by use of a suitable read-out circuit.
2. Summary of the Invention
It is accordingly an object of the invention to provide a semiconductor memory device and a method for fabricating it that overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, whose semiconductor memory elements can store more than one bit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory device formed of a semiconductor substrate having a first conductivity type and a surface. An insulating layer is disposed on the semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in a respective one of the semiconductor memory elements. The bit definition region in a first group of the semiconductor memory elements is a first implantation region disposed at the surface of the semiconductor substrate and has a dopant of the first conductivity type for decreasing the contact resistance. The bit definition region in a second group of the semiconductor memory elements is a second implantation region disposed at the surface of the semiconductor substrate and has a dopant of a second conductivity type for increasing the contact resistance. The bit definition region in a third group of the semiconductor memory elements corresponds to the semiconductor substrate. A further contact region is disposed in the semiconductor substrate outside of the bit definition region. An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.
The idea underlying the invention consists in configuring the respective bit definition region in such a way that it defines the contact resistance between the substrate region and the contact plug region in accordance with the bit to be stored in the respective semiconductor memory element. In other words, the contact hole implantation mask is used for programming, the contact holes being provided with a varying contact resistance. The different resistances can then be assessed during read-out by a suitable evaluation circuit.
The semiconductor memory device according to the invention and the method for fabricating it according to the invention have the following advantages, inter alia, over the known solution approaches. It is possible to realize three-value logic per memory cell using only two implantations. Therefore, for example, three bits can be stored in two cells. This saves a mask plane in comparison with the above-described method that is customary for MOSFETs. The programming does not take place until late in the process after the contact hole etching, which permits a favorable turnaround time. In the case of applications relevant to security, such as e.g. in the smart card field, subsequent read-out by backward preparation is possible only with difficulty.
Finally, no additional steps are necessary in the process sequence because many known overall processes have contact hole implantations in order to reduce the resistance of the contacts to diffusion region, to be precise particularly when titanium silicide or the like is not used. That makes the semiconductor memory device according to the invention and the method for fabricating it according to the invention highly cost-effective.
In accordance with one preferred development, the bit definition region is an implantation region that is located at the surface of the substrate region and serves for setting the contact resistance between the substrate region and the contact plug region. Thus, the contact resistance can be accurately set.
In accordance with a further preferred development, the bit definition region is an implantation region of a dopant of the first conductivity type. This corresponds to a doping on the surface region of the substrate, that is to say, to a decrease in the contact resistance.
In accordance with a further preferred development, the bit definition region is an implantation region of a dopant of a second conductivity type. This corresponds to a counterdoping of the surface region of the substrate, that is to say, to an increase in the contact resistance.
In accordance with a further preferred development, the bit definition region of the semiconductor memory elements corresponds to the substrate region. Thus, it is possible to establish a first state in accordance with a first bit without additional outlay.
In accordance with a further preferred development, the substrate has a further contact region located outside the bit definition region. The further contact region forms a terminal for a simple evaluation circuit, which is additionally connected to the contact plug region in order thus to determine the electrical resistance of the semiconductor memory element.
In accordance with a further preferred development, provision is made of an evaluation circuit device for evaluating the contact resistance of the respective semiconductor memory elements. As indicated above, the evaluation circuit may have a resistance measuring device, but may also operate capacitively or inductively.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a method for fabricating the semiconductor memory device. The method includes the steps of:                a) providing a semiconductor substrate having a first conductivity type;        b) providing an insulating layer on the semiconductor substrate;        c) forming a matrix of contact holes down to the semiconductor substrate in the insulating layer in accordance with respective semiconductor memory elements;        d) providing a surface region of the semiconductor substrate situated underneath each of the contact holes with a contact resistance in accordance with a bit to be stored in a respective semiconductor memory element as a bit definition region of the respective semiconductor memory element, the contact resistance formed by the steps of:                    d1) performing a first implantation with a dopant of the first conductivity type into a first group of the contact holes with remaining ones of the contact holes being masked;            d2) performing a second implantation with a dopant of a second conductivity type into a second group of the contact holes with remaining ones of the contact holes being masked; and            d3) leaving the surface region of the semiconductor substrate situated underneath the respective contact holes in a substrate doping in a third group of contact holes;                        e) providing contact plugs in the contact holes, the contact plugs being in electrical contact with the bit definition region; and        f) providing a further contact region located in the semiconductor substrate outside the bit definition region.        
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory device and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.